The present invention relates, in general, to semiconductor packages, and more particularly, to methods of forming semiconductor packages and structures therefor.
In the past, the semiconductor industry utilized various methods and structures to form packages to encapsulate and provide electrical connections to semiconductor die. Over many years, the configuration of the semiconductor package has evolved with a desire to provide smaller and smaller footprints for the semiconductor packages. In an effort to provide smaller packages, the industry developed various package styles including laminate type packages for example, packages referred to in general as Ball Grid Array (BGA) and Laminate Grid Array (LGA). Other packages styles that provided small footprints and were easy to manufacture included built-up type packages or plated-up type packages such as BCC and Etched Leadless Grid Array (ELGA) packages. An example of an etched leadless grid array (ELGA) type package is provided in United States patent publication number 2005/0263864 of Islam et al that was published on Dec. 1, 2005.
One problem with these prior packages was that once the package was assembled onto an underlying substrate, such as a printed circuit board or other equivalent, it was easy to externally insert an electrical probe between the underlying substrate and the semiconductor package and make electrical contact to the contact terminals on the semiconductor package. Because the contact terminals of the semiconductor package could be electrically probed, it was possible to electrically access the semiconductor die through the electrical probes and to access data that may be stored on the semiconductor die.
Other types of packages, such as those commonly refereed to as Quad Flat Pack (QFN), often had a portion of a lead terminal that was exposed along the side of the package. Such packages could be easily probed to obtain access to information stored in the semiconductor die that was encapsulated within the package.
Accordingly, it is desirable to have a semiconductor package that more securely protects an encapsulated semiconductor die from being electrically probed.
For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor.